1. Field of the Invention
The present invention relates to a solid-state image sensor for sequentially reading out, from one line of a sensor array including an array of pixel photosensor cells or from one of a plurality of lines, which is selected in sequence from the sensor array, signal charge (S) and reset level (N) of the pixel photosensor cells via optical-signal common output lines and noise-signal common output lines and for amplifying and outputting differential signals and further relates to a camera using such a solid-state image sensor and to a camera control system.
The present invention further relates to a signal output device for outputting, from each of plural signal sources, a first signal and a second signal that has a level lower than that of the first signal, reading out the first signals and the second signals via first-signal common output lines and second-signal common output lines, and outputting differential signals between the first signals and the second signals output from the corresponding signal sources.
2. Description of the Related Art
Solid-state image sensors are broadly classified into charge-coupled device (CCD) sensors and metal-oxide semiconductor (MOS) sensors. In general, CCD sensors are advantageous over MOS sensors in that the CCD sensors have less noise, though the CCD sensors are disadvantageous in that their power consumption is large. In contrast, MOS sensors are advantageous over CCD sensors in that the MOS sensors have much smaller power consumption than that of the CCD sensors, though the MOS sensors generally have slightly larger noise. Since the noise in MOS sensors has recently been reduced, it is expected that MOS sensors will achieve a performance equal to or better than that of CCD sensors.
It is relatively easy to provide an MOS sensor with various built-in functional circuits using MOS transistors. As shown in FIG. 7 of Japanese Patent Laid-Open No. 9-246517, performance improvement, such as an increase in processing speed, is achieved by incorporating a plurality of read-out circuits in the MOS sensor.
FIG. 6 schematically shows the configuration of a known MOS sensor. This MOS sensor includes a sensor array 100 including a two-dimensional array of a plurality of pixel photosensor cells 110; a vertical shift register circuit 120 that sequentially selects one row of the pixel photosensor cells 110 from the sensor array 100; line memory circuits 130, each line memory circuit 130 including a signal charge holding capacitor Cts holding signal charge (S) serving as an optical signal and a reset level holding capacitor Ctn holding reset level (N) serving as a noise signal of the corresponding pixel photosensor cell 110 belonging to the selected row; a horizontal shift register circuit 140 that simultaneously selects, using a transfer switch, two pieces of the signal data held in the line memory circuits 130, the signal data being associated with the selected one row, and transfers the selected two pieces of signal data to a first optical-signal common output line (hereinafter referred to as a first S output line) 210 and a first noise-signal common output line (hereinafter referred to as a first N output line) 220 and to a second optical-signal common output line (hereinafter referred to as a second S output line) 230 and a second noise-signal common output line (hereinafter referred to as a second N output line) 240, respectively; and first and second differential-signal (S-N) read-out circuits 150 that amplify and output a first differential signal between an optical signal from the first S output line 210 and a noise signal from the first N output line 220 and a second differential signal between an optical signal from the second S output line 230 and a noise signal from the second N output line 240, respectively.
The first differential signal is output from an output terminal (out1) 170 of the first differential-signal read-out circuit 150, and the second differential signal is output from an output terminal (out2) 180 of the second differential-signal read-output circuit 150. The first S output line 210, the first N output line 220, the second S output line 230, and the second N output line 240 are included in common output lines 160.
In the known MOS sensor shown in FIG. 6, the signal read-out from each line memory circuit 130 to the common output lines 160 is carried out in accordance with a gain determined by a capacitance splitting ratio (Ct/(Ct/Ch)) between a hold capacitance Ct included in the line memory 130 and a capacitance Ch including a wiring capacitance between the common output lines 160 and, primarily, ground, a capacitance between the source and the gate of a MOS switch connected to the common output lines 160, and a capacitance between the source and the backgate of the MOS switch. In other words, the signal charge (S) is read out at the optical-signal common output line in accordance with the gain determined by the capacitance splitting ratio; and the reset level (N) is read out at the noise-signal common output line in accordance with the gain determined by the capacitance splitting ratio. The differential signal between the signal charge (S) and the reset level (N) is output. This differential signal is expressed as A×(Vs×Cts/(Cts+Chs)−Vn×Ctn/(Ctn+Chn)) where A denotes the amplification factor of an amplifier; Vs denotes the optical signal level accumulated in the holding capacitor Cts; and Vn denotes the reset level accumulated in the holding capacitor Ctn.
FIG. 7 is a diagram showing the longitudinal structure of a portion including the common output lines 160 taken along line VII-VII of FIG. 6 showing the known MOS sensor. The first S output line 210, the first N output line 220, the second S output line 230, and the second N output line 240 are arranged, as shown in FIG. 7, in the sequence: the first S output line 210, the first N output line 220, the second S output line 230, and the second N output line 240. Referring to FIG. 7, Ch1s denotes the capacitance of the first optical-signal common output line 210 (hereinafter referred to as the first S output line capacitance); Ch1n denotes the capacitance of the first noise-signal common output line 220 (hereinafter referred to as the first N output line capacitance); Ch2s denotes the capacitance of the second optical-signal common output line 230 (hereinafter referred to as the second S output line capacitance); and Ch2n denotes the capacitance of the second noise-signal common output line 240 (hereinafter referred to as the second N output line capacitance).
In the known MOS sensor shown in FIGS. 6 and 7, the common output lines 160 are arranged in the sequence: the first S output line 210, the first N output line 220, the second S output line 230, and the second N output line 240. Due to a coupling capacitance Cp 250 formed between the first N output line 220 and the second S output line 230, crosstalk is induced between the S-N read-out circuits 150 in opposite directions, resulting in differences in gain, offset, etc. between the S-N read-out circuits 150. These differences in gain, offset, etc. may cause problems.
To describe these problems, FIG. 8 shows an equivalent circuit of a portion of the common output lines 160. FIG. 8 shows a coupling capacitance Cp 310, a first reset level holding capacitor Ct1n 320, a transfer switch (SW) 330, a first N output line capacitance Ch1n 340, and a second S output line capacitance Ch2s 350. The connection between the first reset level holding capacitor Ct1n 320 and the transfer switch 330 has a potential of Vct1n. The connection between the transfer switch 330 and the coupling capacitance Cp 310 has a potential of Vch1n. The connection between the coupling capacitance Cp 310 and the second S output line capacitance Ch2s 350 has a potential of Vch2s.
Due to the crosstalk, charge is injected from the first N output line 220 into the second S output line 230 via the coupling capacitance Cp 310. The state prior to read-out is defined as time t=0, and the time at which the transfer switch SW 330 is activated to start read-out at the common output lines 160 is defined as t=t1. The potentials of the connections at each time are defined as Vct1n (t=0)=Va, Vch1n (t=0)=0, and Vch2s (t=0)=0; and Vct1n (t=t1)=Vch1n (t=t1)=Vb, and Vch2s (t=t1)=Vc. This yields:
                    Vb        =                              Ct1n                          Ct1n              +              Ch1n              +                                                Cp                  ×                  Ch2s                                                  Cp                  ×                  Ch2s                                                              ⁢          Va                                    (        1        )                                Vc        =                              Cp                          Ch2s              +              Cp                                ⁢          Vb                                    (        2        )            In equations (1) and (2), if Ch2s=Ch1n and Cp=αCh1n, then
                                                        Vc              =                                                Cp                                      Ch1n                    +                    Cp                                                  ×                                  Ct1n                                      Ct1n                    +                    Ch1n                    +                                                                  Cp                        ×                        Ch1n                                                                    Cp                        +                        Ch1n                                                                                            ×                Va                                                                                        =                                                α                                      1                    +                    α                                                  ×                                  Ct1n                                      Ct1n                    +                                                                                            1                          +                                                      2                            ⁢                            α                                                                                                    1                          +                          α                                                                    ×                      Ch1n                                                                      ×                Va                                                                        (        3        )            If Ct1n, Ch1n>>α, the following approximations are derived:
                                                                                          α                                      1                    +                    α                                                  ≈                α                            ,                                                          ⁢                                                                    1                    +                                          2                      ⁢                      α                                                                            1                    +                    α                                                  ≈                1                                                                                        Thus              ,                                                          (        4        )                                Vc        =                  α          ×                      Ct1n                          Ct1n              +              Ch1n                                ×          Va                                    (        5        )            In other words, charge is injected into the coupling capacitance Cp, which is α times Ch1n, in accordance with the gain determined by the capacitance splitting ratio between Ct and Ch.
Similarly, due to the crosstalk, charge is injected from the second S output line 230 into the first N output line 220. The potentials of the connections at each time are defined as Vct2s (t=0)=Va′, Vch2s (t=0)=0, and Vch1n (t=0)=0; and Vct2s (t=t1)=Vch2s (t=t1)=Vb′, and Vch1n (t=t1)=Vc′. This yields:
                              Vc          ′                =                  α          ×                      Ct2s                          Ct2s              +              Ch2s                                ×                      Va            ′                                              (        6        )            
At the output terminals 170 and 180, output voltages Vout1 and Vout2 are generated by amplifying the differential signals. These output voltages Vout1 and Vout2 will now be described. To design satisfactory S-N read-out circuits, it is important that Cts=Ctn and Chs=Chn. Assuming that Ct1s=Ct1n=Ct2s=Ct2n=Ct, Ch1s=Ch1n=Ch2s=Ch2n=Ch, and the potentials of the connections when t=0 are Vct1s (t=0)=V1s, Vct1n (t=0)=V1n, Vct2s (t=0)=V2s, and Vct2n (t=0)=V2n, then Vout1 and Vout2 are estimated as:
                                                                                                              Vout1                    =                                          A                      ×                                              (                                                                                                            Ct1s                                                              Ct1s                                +                                Ch1s                                                                                      ×                            V1s                                                    -                                                      (                                                                                                                            Ct1n                                                                      Ct1n                                    +                                    Ch1n                                                                                                  ×                                V1n                                                            +                                                              α                                ×                                                                  Ct2s                                                                      Ct2s                                    +                                    Ch2s                                                                                                  ×                                V2s                                                                                      )                                                                          )                                                                                                                                                              =                                          A                      ×                                              Ct                                                  Ct                          +                          Ch                                                                    ×                                              (                                                  V1s                          -                                                      (                                                          V1n                              +                                                              α                                ×                                V2s                                                                                      )                                                                          )                                                                                                                                                                                                                                                Vout2                      =                                                                        A                          ×                                                      (                                                                                                                            Ct2s                                                                      Ct2s                                    +                                    Ch2s                                                                                                  ×                                V2s                                                            +                                                              α                                ×                                                                  Ct1n                                                                      Ct1n                                    +                                    Ch1n                                                                                                  ×                                V1n                                                                                      )                                                                          -                                                                              Ct2n                                                          Ct2n                              +                              Ch2n                                                                                ×                          V2n                                                                                      )                                                                                                                    =                                          A                      ×                                              Ct                                                  Ct                          +                          Ch                                                                    ×                                              (                                                                              (                                                          V2                              +                                                              α                                ×                                V1n                                                                                      )                                                    -                          V2n                                                )                                                                                                                                                    (        7        )            The coupling capacitance Cp 250 formed between the two common output lines Ch1n 220 and Ch2s 230 generates the crosstalk between the S-N read-out circuits 150 in opposite directions. As a result, the gain difference, the offset difference, etc. are induced between the S-N read-out circuits 150. In other words, equations (7) show that Vout1 induces crosstalk in the negative direction, which is expressed as A×(Ct/(Ct+Ch))×(−α×V2s), and Vout2 induces crosstalk in the positive direction, which is expressed as A×(Ct/(Ct+Ch))×(α×V1n).
To alleviate the crosstalk between the S-N read-out circuits 150, (1) a large wiring distance is allowed between the common output lines 160, and (2) shield lines to which a ground potential is supplied are disposed between the common output lines 160. However, (1) the wiring region of the common output lines 160 becomes large, resulting in an increase in the chip size; and (2) the gain determined by the capacitance splitting ratio between Ct and Cn is reduced, resulting in reduction of the signal level and relative degradation of the S/N ratio.